In Radio Frequency (RF) applications, higher and higher characteristic frequencies of the device are being required. Although RFCMOSs (Radio-Frequency Complementary Metal-Oxide Semiconductors) can realize higher characteristic frequencies in advanced technologies, they can hardly reach characteristic frequencies higher than 40 GHz and always lead to high costs in development of advanced technologies. For this reason, devices such as RFCMOSs made in advanced technologies are not able to completely meet the RF requirements. Although devices made by using compound semiconductors can realize extremely high characteristic frequencies, they have disadvantages of high cost of materials and small sizes. Besides, most of the compound semiconductors are toxic. Therefore, their applications are limited. In contrary, SiGe (Silicon-Germanium) HBTs (Heterojunction Bipolar Transistors) are good choices for, as well as the mainstream of, ultra-high-frequency devices for the following reasons. Firstly, they take advantage of the difference between energy bands of strained SiGe and strained Si to generate a strain effect, which can alter properties of materials, thereby improving carriers injection efficiency of emitter-region and thus increasing the current magnification of the device. Secondly, a lower base resistance and a higher characteristic frequency can be achieved through a heavily doped SiGe base region. Thirdly, the SiGe process is basically compatible with the silicon process. Based on the above merits, output devices are required to have better performances, such as a higher current gain (no less than 15) and a higher cut-off frequency (no less than 1 GHz).
In existing silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs), a heavily doped collector buried layer is formed to lower the collector resistance and deep trench isolations are formed to reduce a parasitic capacitance between the collector region and the substrate, so as to improve their frequency characteristics. The existing SiGe HBTs can adopt a parasitic lateral PNP structure. FIG. 1 is an electrical schematic diagram of an existing parasitic lateral PNP transistor, in which the base, emitter and collector are connected to the base, emitter and collector regions, respectively. Although the fabrication process for the existing parasitic lateral PNP transistor is mature and reliable, it still has shortcomings, mainly as follows: 1) an L-shaped path for the base current Ic results in poor current amplification capacity and poor frequency characteristics of the device; 2) the feature of picking up the base region from a side of the device results in the increase of the device area; 3) the collector region is formed by using an epitaxial growing process which has a high costs; 4) the adopted deep trench isolation process is complex and has a relatively high cost.